1. Field of the Invention
The present invention relates to a stacked-type semiconductor device in which a plurality of semiconductor elements are stacked and to a fabrication method thereof.
2. Description of the Related Art
Miniaturized thin stacked-type semiconductor devices in which a plurality of semiconductor elements are stacked, such as semiconductor devices in which a plurality of semiconductor memories are installed, are in demand in keeping with the expansion of the functions of small and lightweight portable information devices and so forth.
First, a first conventional example disclosed in Japanese Unexamined Patent Publication No. 2002-270763 (a semiconductor device in which a semiconductor carrier electrode and an upper semiconductor element electrode are connected by means of a fine metal wire) will be described with reference to FIGS. 23A and 23B.
The semiconductor device disclosed in the first conventional example is such that the surface of a first semiconductor element 53, which has bumps 56 formed on surface electrodes, is oriented downward and the semiconductor element 53 is joined to a semiconductor carrier 51, which is a multilayered circuit wiring substrate. A plurality of first electrodes 62 for conduction with the first semiconductor element 53 and a second plurality of electrodes 52 for conduction with a second semiconductor element 58 are formed on the upper surface of the semiconductor carrier 51. Further, this plurality of first electrodes 62 and the bumps 56 that are formed on the first semiconductor element 53 are joined by means of conductive adhesive 65. This conductive adhesive 65 is supplied to the bumps 56 beforehand. Further, underfill material 54 is made to fill and insulate the gap between the mutually joined first semiconductor element 53 and semiconductor carrier 51. In addition, a second semiconductor element 58 is bonded via die-bonding material 57 to the rear face (the upper face in FIG. 23A) of the first semiconductor element 53 such that the second semiconductor element 58 and first semiconductor element 53 are stacked. Further, wire bonding is used to connect electrically bonding pads 59 on the second semiconductor element 58 and a plurality of second electrodes 52 on the upper face of the semiconductor carrier 51 to one another via fine metal wires 60. In addition, an insulating sealing resin 63 is made to fill and seal the wiring portion of the fine metal wires 60 and the periphery of the first semiconductor element 53 between the second semiconductor element 58 and semiconductor carrier 51. Finally, external terminal electrodes 61 are mounted on the lower face (external face) of the semiconductor carrier 51.
Next, a second conventional example disclosed in Japanese Unexamined Patent Publication No. 2003-347505 (a semiconductor device in which inner leads are adopted in place of the fine metal wires that are used in the first conventional example) will now be described with reference to FIGS. 24A and 24B.
The semiconductor device disclosed in the second conventional example has a first semiconductor element 73, a second semiconductor element 78, and a tape carrier 71 stacked and arranged in the same package. Further, the tape carrier 71 and the semiconductor elements 73 and 78 are electrically connected by means of inner leads 75 of the tape carrier 71. That is, a plurality of lands 72 is formed on an array that is provided on the surface of the tape carrier 71 and external terminal electrodes 81 are mounted on the lands 72. Further, the inner leads 75, which extend from the lands 72, are each bonded to electrode pads 74 of the first semiconductor element 73 and/or to the electrode pads 79 provided on the upper-face perimeter of the second semiconductor element 78. In addition, sealing resin 83 is made to fill from the upper face of the second semiconductor element 68 to the outer perimeter of the tape carrier 71, whereby the inner leads 75 and bonding pads 74 and 79 are protected.
However, the semiconductor device of the first conventional example includes factors that obstruct miniaturization. That is, the semiconductor device uses wire bonding to connect the bonding pads 59 of the second semiconductor element 58 to the second electrodes 52 of the semiconductor carrier 51. In a case where the connections are made by using wiring bonding, as shown in FIG. 23B, a sealing fill region (bonding area) 70, which is filled by means of insulating sealing resin 63, must be provided at least as far as the outside of the second semiconductor element 58 so that the fine metal wires 60 jut out further than the outer edge of the second semiconductor element 58. Hence, the mounting area is larger than that of the second semiconductor element 58, which is an impediment to miniaturization of the semiconductor device.
There has also been a problem that because the first semiconductor element 53 and second semiconductor element 58 are completely sealed with resin, the semiconductor device is caused to be inferior in heat radiation.
In addition, the semiconductor device of the second conventional example above includes factors obstructing an increased number of pins (a greater number of the external terminal electrodes 81). That is, with the semiconductor device, the semiconductor elements 73 and 78, which are arranged stacked in the same package, are electrically connected to the lands 72 by means of the inner leads 75. Hence, the number of lands 72 arranged is limited by the amount of wiring of the inner leads 75. Further, there must be a smaller number of mounting parts of the semiconductor elements 73 and 78 than the semiconductor device. The above factors obstruct any increase in the number of pins of the semiconductor device.